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BH1750FVI
Technical Note
● Application circuit example of DVI terminal
The DVI terminal is an asynchronous reset terminal. Please note that there is a possibility that IC doesn't operate normally
if the reset section is not installed after the start-up of V CC .
(Please refer to the paragraph of "Timing chart for V CC and DVI power supply sequence" )
The description concerning SDA and the terminal SCL is omitted in this application circuit example. Please design the
application the standard of the I2C bus as it finishes being satisfactory. Moreover, the description concerning the terminal
ADDR is omitted. Please refer to the paragraph of "Timing chart for V CC and DVI power supply sequence" about the terminal
ADDR design.
ex 1) The control signal line such as CPU is connected.
BH1750FVI
VCC
SCL
Micro
0.1μF
ADDR
DVI
0.1μF
Controller
GND
SDA
ex 2) Reset IC is used.
1, For Reset IC of the Push-Pull type
BH1750FVI
VCC
SCL
0.1μF
ADDR
DVI
0.1μF
RESET
GND
SDA
Reset IC( Push-Pull type )
2, For Reset IC of the Open drain output
BH1750FVI
1kOhm
VCC
SCL
0.1μF
ADDR
DVI
0.1μF
RESET
ex 3) A different power supply is used.
GND
VCC
SDA
BH1750FVI
SCL
Reset IC( Open drain type )
0.1μF
V1
ADDR
DVI
GND
SDA
V2
0.1μF
※ Power supply of DVI must stand up later than power supply of VCC stand up, because it is necessary to secure reset section ( 1μs or more ).
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? 2011 ROHM Co., Ltd. All rights reserved.
8/17
2011.11 - Rev.D
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